Recently, a demand for liquid crystal display devices for use in large-screen liquid crystal display (LCD) TV sets as well as for use in portable telephones (such as mobile phones or cellular phones), notebook PCs, and monitors has expanded. As these liquid crystal display devices, an active matrix driving LCD device capable of performing high-definition display is employed. First, referring to FIG. 6, a typical configuration of the active matrix driving LCD device will be outlined. FIG. 6 schematically shows a main configuration connected to a pixel in a liquid crystal display unit, using an equivalent circuit.
Generally, a display unit 960 of the active matrix driving LCD device includes a semiconductor substrate, an opposing substrate, and a liquid crystal sealed in between these two substrates by opposing these two substrates. On the semiconductor substrate, transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are arranged in a matrix form (of 1280×3 pixel rows×1024 pixel columns in the case of a color SXGA panel, for example). One transparent electrode 967 is formed on an entire surface of the opposing substrate.
Turning on and off of a TFT 963 having a switching function is controlled by a scan signal. When the TFT 963 is turned on, a gray scale signal voltage corresponding to a video data signal is applied to a corresponding pixel electrode 964. Transmittance of the liquid crystal is changed by a potential difference between each pixel electrode 964 and the opposing substrate electrode 967, and even after the TFT 963 has been turned off, the potential difference is held by a liquid crystal capacitance 965 and an auxiliary capacitance 966 for a certain period, thereby displaying an image.
On the semiconductor substrate, data lines 962 and scan lines 961 are wired in the form of a grid (in which 1280×3 data lines and 1024 scan lines are arranged in the case of the color SXGA panel described above). A data line 962 sends a plurality of level voltages (gray scale signal voltages) applied to each pixel electrode 964, and a scan line 961 sends the scan signal. Due to a capacitance produced at an intersection between each of the scan lines 961 and each of the data lines 962 and a liquid crystal capacitance sandwiched between the semiconductor substrate and the opposing substrate, the scan lines 961 and the data lines 962 have become a large capacitive load.
The scan signal is supplied to a scan line 961 from a gate driver 970, and a grayscale signal voltage is supplied to each pixel electrode 964 from a data driver 980 through a data line 962. The gate driver 970 and the data driver 980 are controlled by a display controller 950. A clock CLK, a control signal, and a voltage supply that are necessary are supplied from the display controller 950 to each of the gate driver 970 and the data driver 980, and video data is supplied to the data driver 980. Currently, digital data is beginning to be wide spread used as the video data.
Rewriting of data of one screen is performed in one frame period (of approximately 0.017 seconds, usually). Data is successively selected every pixel row (every line) by each scan line, and a gray scale voltage signal is supplied from each data line within a selection period.
While the gate driver 970 needs to supply the scan signal of at least binary values, the data driver 980 needs to drive a data line by the gray scale voltage signal of multi-valued levels in accordance with the number of gray scales. For this reason, the data driver 980 includes a decoder that converts the video data to an analog voltage and a digital-to-analog converter circuit (DAC) formed of an output amplifier that amplifies the analog voltage and outputs the amplified analog voltage to a corresponding data line 962.
As a method of driving a large-screen display device such as a LCD TV, a dot inversion driving scheme capable of providing high image quality is adopted. The dot inversion driving scheme is the driving scheme in which an opposing substrate electrode voltage VCOM is set to a constant voltage and voltage polarities held in adjacent pixels are mutually opposite in the display panel 960 in FIG. 6. For this reason, polarities of voltages output to the adjacent data lines (962) become positive-polarity and negative-polarity with respect to the opposing substrate electrode voltage VCOM. The data driver 980 in the dot inversion driving scheme must output positive-polarity and negative-polarity gray scale signal voltages, at least two voltage supplies having a potential difference which is approximately twice of the maximum value of a liquid crystal application voltage (that is a potential difference between a gray scale voltage and the opposing substrate electrode voltage) are supplied to the output amplifier of the data driver.
FIG. 7 is a diagram showing an example of a typical configuration of an output circuit (composed by a positive-polarity amplifier, a negative-polarity amplifier, and an output switch circuit) for two outputs in a data driver that performs dot inversion driving. In FIG. 7, two adjacent data lines are connected to driver output terminals P1 and P2. The output circuit in FIG. 7 includes a positive-polarity amplifier 91, a negative-polarity amplifier 92, and an output switch circuit 30. To the positive-polarity amplifier 91, a high-potential voltage supply VDD2 and a low-potential voltage supply VSS are provided. Based on a positive-polarity reference voltage V11, the positive-polarity amplifier 91 performs amplification and outputs a positive-polarity gray scale voltage Vout1 to an amplifier output terminal N11. To the negative-polarity amplifier 92, the high-potential voltage supply VDD2 and the low-potential voltage supply VSS are provided. Based on a negative-polarity reference voltage V21, the negative-polarity amplifier 92 performs amplification and outputs a negative-polarity gray scale voltage Vout2 to an amplifier output terminal N12. The opposing substrate electrode voltage VCOM is set to be close to an intermediate voltage between the high-potential voltage supply VDD2 and the low-potential voltage supply VSS.
The positive-polarity amplifier 91 includes a current source M15 with a first terminal thereof connected to a low-potential voltage supply VSS, an N-channel differential pair (M11, M12) with coupled sources thereof connected to a second terminal of the current source M15, a current mirror (M13, M14) connected between an output pair of the N-channel differential pair (M11, M12) and a high-potential voltage supply VDD2, an amplifying transistor M16 connected between the high-potential voltage supply VDD2 and the amplifier output terminal N11, and a current source M17 connected between the low-potential voltage supply VSS and the amplifier output terminal N11. An output terminal of the current mirror (a connection node between a drain of the N-channel transistor M12 and a drain of the P-channel transistor M14) is connected to a gate of the amplifying transistor M16. The positive-polarity amplifier 91 has a voltage follower configuration in which the positive-polarity reference voltage V11 is supplied to a non-inverting input terminal (a gate of the transistor M12) of the N-channel differential pair (M11, M12) and an inverting input terminal (a gate of the transistor M11) of the N-channel differential pair (M11, M12) is connected to the amplifier output terminal N11. Since the positive-polarity reference voltage V11 is a voltage signal indicative of a voltage between the voltage VCOM and the high-potential voltage supply VDD2, the positive-polarity amplifier 91 in FIG. 7 can be implemented with a simple configuration using the differential pair of a single polarity and with a saved area.
The negative-polarity amplifier 92 has a configuration of a polarity reverse to that of the positive-polarity amplifier 91. The negative-polarity amplifier 92 includes a current source 25 with a first terminal thereof connected to the high-potential voltage supply VDD2, a P-channel differential pair (M21, M22) with coupled sources thereof connected to a second terminal of the current source M25, a current mirror (M23, M24) connected between an output pair of the P-channel differential pair (M21, M22) and the low-potential voltage supply VSS, an amplifying transistor M26 connected between the low-potential voltage supply VSS and the amplifier output terminal N12, and a current source M27 connected between the high-potential voltage supply VDD2 and the amplifier output terminal N12. An output terminal of the current mirror (a connection node between a drain of the P-channel transistor M22 and a drain of the N-channel transistor M24) is connected to a gate of the amplifying transistor M26. The negative-polarity amplifier 92 has a voltage follower configuration in which the negative-polarity reference voltage V21 is supplied to a non-inverting input terminal (a gate of the transistor M22) of the P-channel differential pair (M21, M22) and an inverting input terminal (a gate of the transistor M23) of the N-channel differential pair (M21, M22) is connected to the amplifier output terminal N12. Since the negative-polarity reference voltage V21 is a voltage signal indicative of a voltage between the voltage VCOM and the low-potential voltage supply VSS, the negative-polarity amplifier 92 can be implemented with a simple configuration using the differential pair of a single polarity and with a saved area.
The output switch circuit 30 includes switches controlled by control signals S1 and S2. When switches SW11 and SW22 controlled by the control signal S1 are turned on, the amplifier output terminals N11 and N12 are connected to the driver output terminals P1 and P2, respectively. Then, the output voltage Vout1 of the positive-polarity amplifier 91 and the output voltage Vout2 of the negative-polarity amplifier 92 are output to the driver output terminals P1 and P2, respectively.
When switches SW12 and SW21 controlled by the control signal S2 are turned on, the amplifier output terminals N11 and N12 are connected to the driver output terminals P2 and P1, respectively. Then, the output voltage Vout1 of the positive-polarity amplifier 91 and the output voltage Vout2 of the negative-polarity amplifier 92 are output to the driver output terminals P2 and P1, respectively.
In the dot inversion driving scheme in recent times, in order to reduce power consumption, a driving method is being carried out where polarities of just N pixels in a pixel column in a date line direction are set to be the same (which is driving for dot inversion for each N horizontal periods). In this case, though polarities of voltages of adjacent data lines are reverse to each other, polarities of voltages of the N pixels output to a same data line become identical.
In the dot inversion driving scheme for each horizontal period, a positive-polarity reference signal and a negative-polarity reference signal are alternately output to a same data line. Thus, a charging operation is always performed when the positive-polarity reference signal is output, while a discharging operation is always performed when the negative-polarity reference signal is output.
In the dot inversion driving for each N horizontal periods, N gray scale signals of a same polarity are output to a same data line. Thus, the discharging operation becomes necessary even when the positive-polarity reference signal is output and the charging operation becomes necessary even when the negative-polarity reference signal is output.
That is, it becomes necessary for each of the positive-polarity amplifier 91 and the negative-polarity amplifier 92 to have both sufficient charging and discharging capabilities.
The positive-polarity amplifier 91 in FIG. 7 performs the discharging operation using the current source M17, while the negative-polarity amplifier 92 in FIG. 7 performs the charging operation using the current source M27. Thus, discharging capability of the positive-polarity amplifier 91 and charging capability of the negative-polarity amplifier 92 are usually poor. In order to enhance the discharging capability of the current source M17 and the charging capability of the current source M27, respective current values of the current sources need to be increased. However, a problem that static power consumptions of the amplifiers increase may thereby arise. On the other hand, as an amplifier configuration in which the static power consumption of the amplifier can be reduced and each of the discharging capability of the positive-polarity amplifier 91 and the charging capability of the negative-polarity amplifier 92 is high, an AB class circuit in Patent Document 1 listed later, for example, can be employed.
FIG. 8 is a diagram showing a configuration of the AB class output circuit in Patent Document 1. An output stage is composed of a P-channel transistor M85 connected between a high-potential voltage supply VDD and an output terminal Vout and an N-channel transistor M86 connected between the output terminal Vout and a low-potential voltage supply VSS. The output stage has high charging and discharging capabilities with respect to the output terminal Vout. A gate NP1 of the P-channel transistor M85 is connected to an output of a driver 89 that has received an input signal Vin, and the P-channel transistor M85 performs a charging operation. A change in the input signal Vin is transferred to a gate NN1 of the N-channel transistor M86 via an intermediate stage (M81, M82), and the N-channel transistor M86 performs a discharging operation. The intermediate stage is formed of a P-channel floating current source M81, an N-channel floating current source M82, and current sources M83 and M84. A bias voltage BP8 is applied to a gate of the P-channel floating current source M81, and a bias voltage BN8 is applied to a gate of the N-channel floating current source M82. The P-channel floating current source M81 and the N-channel floating current source M82 are connected between the gate (NP1) of the transistor M85 and the gate (NN1) of the transistor M86. The current source M83 is connected between the high-potential voltage supply VDD and the gate NP1 of the P-channel transistor M85, while the current source M84 is connected between the low-potential voltage supply VSS and the gate NN1 of the N-channel transistor M86. A sum of currents of the floating current sources M81 and M82 is set to be substantially the same as a current of each of the current sources M83 and M84.
An operation of the AB class output circuit in FIG. 8 will be described. When a potential of the terminal NP1 is changed to low in response to an input voltage Vin, the P-channel transistor M85 performs the charging operation. In this case, a current of the N-channel floating current source M82 does not change, but a current of the P-channel floating current source 81 is reduced. Thus, a potential of the terminal NN1 is changed to low, so that the discharging operation of the N-channel transistor M86 is stopped. Accordingly, the AB class output circuit in FIG. 8 can perform the charging operation at high speed.
On the other hand, when the potential of the terminal NP1 is changed to high in response to the input voltage Vin, the charging operation of the P-channel transistor M85 is stopped. In this case, the current of the N-channel floating current source M82 does not change, but the current of the P-channel floating current source 81 is increased. Thus, the potential of the terminal NN1 is changed to high, so that the N-channel transistor M86 performs the discharging operation. Accordingly, the AB class output circuit in FIG. 8 can perform the discharging operation at high speed.
When a relationship between the sum of currents of the floating current sources M81 and M82 and the current of each of the current sources M83 and M84 is maintained, current values of the respective current sources can be reduced sufficiently.
According to Patent Document 2 listed below, which has cited Patent Document 1, the driver 89 can be formed of an N-channel differential pair. In this case, the AB class output circuit in FIG. 8 can be replaced by the positive-polarity amplifier 91 in FIG. 7.
Further, when an output terminal of the driver 89 is configured to be connected to the terminal NN1 and the driver 89 is formed of a P-channel differential pair, the AB class output circuit can also be replaced by the negative-polarity amplifier 92 in FIG. 7.
[Patent Document 1]
JP Patent Kokoku Publication No. JP-B-6-91379 (FIG. 1)
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2005-124120A (FIG. 1)